MARC details
000 -LEADER |
fixed length control field |
01344nmm a22003017a 4500 |
003 - CONTROL NUMBER IDENTIFIER |
control field |
SPU |
005 - DATE AND TIME OF LATEST TRANSACTION |
control field |
20210709133944.0 |
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
fixed length control field |
210520b2019 sz |||||o|||| 00| 0 eng d |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
International Standard Book Number |
9783030136055 (E-book) |
040 ## - CATALOGING SOURCE |
Original cataloging agency |
SPU |
Transcribing agency |
SPU |
050 #4 - LIBRARY OF CONGRESS CALL NUMBER |
Classification number |
TK 7868.L6 |
Item number |
L35I 2019 |
100 ## - MAIN ENTRY--PERSONAL NAME |
Personal name |
LaMeres, Brock J. |
9 (RLIN) |
241044 |
245 10 - TITLE STATEMENT |
Title |
Introduction to logic circuits & logic design with Verilog / |
Statement of responsibility, etc. |
Brock J. LaMeres |
Medium |
[electronic resource] |
250 ## - EDITION STATEMENT |
Edition statement |
Second edition |
260 ## - PUBLICATION, DISTRIBUTION, ETC. |
Place of publication, distribution, etc. |
Cham, Switzerland : |
Name of publisher, distributor, etc. |
Springer, |
Date of publication, distribution, etc. |
2019 |
300 ## - PHYSICAL DESCRIPTION |
Extent |
1 online resource (xvi, 485 pages) : |
Other physical details |
illustrations (some color) |
449 ## - DEPARTMENT (SPU) |
Department name |
บางเขน. คณะวิศวกรรมศาสตร์. วิศวกรรมไฟฟ้า |
449 ## - DEPARTMENT (SPU) |
Department name |
บางเขน. คณะเทคโนโลยีสารสนเทศ. วิศวกรรมคอมพิวเตอร์ |
505 0# - FORMATTED CONTENTS NOTE |
Formatted contents note |
Introduction : Analog Vs. digital -- Number systems -- Digital circuitry & interfacing -- Combinational logic design -- Verilog (Part 1) -- MSI logic -- Sequential logic design -- Verilog (Part 2) -- Behavioral modeling of sequential logic -- Memory -- Programmable logic -- Arithmetic circuits -- Computer system design |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name entry element |
LOGIC CIRCUITS |
9 (RLIN) |
34876 |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name entry element |
LOGIC DESIGN |
9 (RLIN) |
35741 |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name entry element |
VERILOG (COMPUTER HARDWARE DESCRIPTION LANGUAGE) |
9 (RLIN) |
91785 |
850 ## - HOLDING INSTITUTION |
Holding institution |
SPU |
856 40 - ELECTRONIC LOCATION AND ACCESS |
Uniform Resource Identifier |
<a href="https://drive.google.com/file/d/15iKZ6F3TabLTzyKS-5jh7OisWgOwab4E/view?usp=sharing">https://drive.google.com/file/d/15iKZ6F3TabLTzyKS-5jh7OisWgOwab4E/view?usp=sharing</a> |
Link text |
View Full-text |
910 ## - ACQUISITION INFORMATION (SPU) |
Purchaser |
Library |
Publisher |
Springer |
Accession date |
200521 |
942 ## - ADDED ENTRY ELEMENTS (KOHA) |
Source of classification or shelving scheme |
Library of Congress Classification |
Koha item type |
E-Book |
998 ## - STAFF NAME (SPU) |
ผู้ลงรายการ |
niparat 0521 |